The uplink DPDCH and DPCCH are I/Q code multiplexed. But the downlink DPDCH and DPCCH is time multiplexed. This is main difference.

Basically, there are two types of downlink DPCH. They are distinguished by the use or non use of the TFCI field. TFCI bits are not used for fixed rate services or when the TFC doesn’t change.

  • Downlink DPDCH and DPCCH is time division multiplexing (TDM).
  • DPDCH carries data generated at Layer 2 and higher layer
  • DPCCH carries control information generated at Layer 1
  • SF of downlink DPCH is from 512 to 4

Frame Structure of Downlink DPCH (DPDCH+DPCCH)

Frame Structure of Downlink DPCH

We have known that the uplink DPDCH and DPCCH are I/Q code multiplexed. But the downlink DPDCH and DPCCH is time multiplexed. This is main difference. The parameter k in the figure above determines the total number of bits per time slot. It is related to the SF, which ranges from 4 to 512. The chips of one slot is also 2560.

Downlink physical channels are used to carry user specific information like speech, data or signaling, as well as layer 1 control bits. Like it was mentioned before, the payload from the DPDCH and the control bits from the DPCCH are time multiplexed on every time slot. The figure above shows how these two channels are multiplexed. There is only one DPCCH in downlink for one user.